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dsPIC30F3010/3011

DS70141F-page 22

2010 Microchip Technology Inc.

2.3

Divide Support

The dsPIC DSC devices feature a 16/16-bit signed

fractional divide operation, as well as 32/16-bit and 16/

16-bit signed and unsigned integer divide operations, in

the form of single instruction iterative divides. The

following instructions and data sizes are supported:

DIVF

– 16/16 signed fractional divide

DIV.sd

– 32/16 signed divide

DIV.ud

– 32/16 unsigned divide

DIV.sw

– 16/16 signed divide

DIV.uw

– 16/16 unsigned divide

The divide instructions must be executed within a

REPEAT

loop. Any other form of execution (e.g. a series

of discrete divide instructions) will not function correctly

because the instruction flow depends on RCOUNT. The

divide instruction does not automatically set up the

RCOUNT value, and it must, therefore, be explicitly and

correctly specified in the REPEAT instruction, as shown

in Table 2-1 (REPEAT will execute the target instruction

{operand value + 1} times). The REPEAT loop count

must be set up for 18 iterations of the DIV/DIVF

instruction. Thus, a complete divide operation requires

19 cycles.

TABLE 2-1:

DIVIDE INSTRUCTIONS

2.4

DSP Engine

The DSP engine consists of a high-speed 17-bit x

17-bit multiplier, a barrel shifter, and a 40-bit adder/

subtracter (with two target accumulators, round and

saturation logic).

The dsPIC30F devices have a single instruction flow

which can execute either DSP or MCU instructions.

Many of the hardware resources are shared between

the DSP and MCU instructions. For example, the

instruction set has both DSP and MCU multiply

instructions which use the same hardware multiplier.

The DSP engine also has the capability to perform

inherent accumulator-to-accumulator operations, which

require no additional data. These instructions are ADD,

SUB

and NEG.

The DSP engine has various options selected through

various bits in the CPU Core Configuration register

(CORCON), as listed below:

Fractional or integer DSP multiply (IF).

Signed or unsigned DSP multiply (US).

Conventional or convergent rounding (RND).

Automatic saturation on/off for ACCA (SATA).

Automatic saturation on/off for ACCB (SATB).

Automatic saturation on/off for writes to data

memory (SATDW).

Accumulator

Saturation

mode

selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-2.

Note:

The divide flow is interruptible. However,

the user needs to save the context as

appropriate.

Instruction

Function

DIVF

Signed fractional divide: Wm/Wn

→ W0; Rem → W1

DIV.sd

Signed divide: (Wm + 1:Wm)/Wn

→ W0; Rem → W1

DIV.sw

Signed divide: Wm/Wn

→ W0; Rem → W1

DIV.ud

Unsigned divide: (Wm + 1:Wm)/Wn

→ W0; Rem → W1

DIV.uw

Unsigned divide: Wm/Wn

→ W0; Rem → W1

TABLE 2-2:

DSP INSTRUCTION

SUMMARY

Instruction

Algebraic Operation

CLR

A = 0

A = (x – y)2

EDAC

A = A + (x – y)2

MAC

A = A + (x y)

MOVSAC

No change in A

MPY

A = x y

MPY.N

A = – x y

MSC

A = A – x y

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